AN4069

ENABLE/FAULT pin, thermal latch

Doc ID 022926 Rev 1

7/16

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ENABLE/FAULT pin, thermal latch

The board provides for separate or linked ENABLE pins, in order to allow either the

observation of each single E-fuse or the complete 5 V/12 V protection application. The Q1

MOSFET mounted on the board is connected to the 5 V device ENABLE pin only. This open

drain circuit can be used to remotely control the device reset, by biasing the GATE pin with a

positive voltage (5-10 V).

If this feature is not used, the MOSFET gate should be kept at GND (jumper on Cn4 pins 4-

5). In this way the MOSFET does not influence the ENABLE/FAULT pin. To obtain a

simultaneous shutdown and reset of both the devices, in the case of a thermal fault event on

one of them, pins 2-3 of CN4 can be shorted together.

The devices can be reset from a thermal latch status also by re-cycling the power supply.

The following diagram shows the ENABLE/FAULT pin signal levels in all the operating

modes.

Figure 5.

ENABLE/FAULT pin status

A thermal fault event can occur in the case of overload, short-circuit on the output or, under

certain dissipation conditions, in the case of overvoltage on the input, causing a voltage

clamp. In such cases the device output is disconnected, the ENABLE/FAULT pin is driven

into an intermediate voltage level (~1.4 V) and the system is latched in this status. A reset

V), and then releasing it again.

The same effect can be obtained by re-cycling the power supply to the board.