AN2281 datasheet(7/38 Pages) STMICROELECTRONICS

7 / 38 page

AN2281

Implementation on the ST7LITE35 microcontroller

7/38

In dual timer mode, PWM2 and PWM3 can be generated with a different frequency

controlled by CNTR2 and ATR2.

The duty cycle is selected by programming the DCRx registers. These are preload registers.

The DCRx values are transferred in active duty cycle registers after an overflow event if the

corresponding transfer bit (TRANx bit) is set.

The TRAN1 bit controls the PWMx outputs driven by counter 1 and the TRAN2 bit controls

the PWMx outputs driven by counter 2.

PWM generation and output compare are done by comparing these active DCRx values

with the counter.

Figure 5.

The dual 12-bit autoreload timer: dual timer mode (ENCNTR2=1)

At reset, the counter starts counting from 0. When an upcounter overflow occurs (OVF

event), the preloaded Duty cycle values are transferred to the active Duty Cycle registers

and the PWMx signals are set to a high level. When the upcounter matches the active DCRx

value the PWMx signals are set to a low level. To obtain a signal on a PWMx pin, the

contents of the corresponding active DCRx register must be greater than the contents of the

ATR register.

The polarity bits can be used to invert any of the four output signals. The inversion is

synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2

The PWMx output signals can be enabled or disabled using the OEx bits in the PWMCR

PWM0

PWM1

PWM2

PWM3

Dead Time

Generator

PWM3 Duty Cycle Generator

12-bit Input Capture

12-Bit Autoreload Register 2

12-Bit Upcounter 2

PWM2 Duty Cycle Generator

PWM1 Duty Cycle Generator

PWM0 Duty Cycle Generator

12-Bit Autoreload Register 1

12-Bit Upcounter 1

Clock

Control

Output Compare

CMP

Interrupt

OVF1 interrupt

OVF2 interrupt

Edge Detection Circuit

OE0

OE1

OE2

OE3

ATIC

DTE bit

BPEN bit

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