UPD703003 datasheet(52/82 Pages) NEC

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µPD703003

Data Sheet U12261EJ2V1DS00

Instruction Mnemonic

Operand

Opcode

Operation

Flags

group

CY OV SZ SAT

Special

LDSR

reg2, regID

r r r r r 1 1 1 1 1 1 RRRRR SR[regID]

← GR[reg2] regID = EIPC, FEPC

instructions

00 000 0 00 001 0 00 00

regID = EIPSW, FEPSW

Note

regID = PSW

× × ×××

STSR

regID, reg2

r r r r r 1 1 1 1 1 1 RRRRR GR[reg2]

← SR[regID]

00 000 0 00 010 0 00 00

TRAP

vector

00 000 1 11 111 i i i i i

EIPC

← PC + 4 (restored PC)

00 000 0 01 000 0 00 00 EIPSW

← PSW

ECR.EICC

← Interrupt code

PSW.EP

← 1

PSW.ID

← 1

← 00000040H (when vector is 00H to 0FH)

00000050H (when vector is 10H to 1FH)

RETI

00 000 1 11 111 0 00 00 if PSW.EP = 1

R R R R

00 000 0 01 010 0 00 00

then PC

← EIPC

PSW

← EIPSW

else if PSW.NP = 1

then PC

← FEPC

PSW

← FEPSW

else PC

← EIPC

PSW

← EIPSW

HALT

00 000 1 11 111 0 00 00 Stops

00 000 0 01 001 0 00 00

00 000 1 11 111 0 00 00 PSW.ID

← 1

00 000 0 01 011 0 00 00 (maskable interrupt prohibit)

10 000 1 11 111 0 00 00 PSW.ID

← 0

00 000 0 01 011 0 00 00 (maskable interrupt enable)

NOP

00 000 0 00 000 0 00 00 No operation, uses at least one clock

Note In this instructions, “reg2” is the mnemonic abbreviation for the source register, but the reg1 field is used

for the opcode. Consequently, these instructions differ from other instructions in a way registers are

specified in mnemonics description and opcodes.

rrrrr = regID specification

RRRRR = reg2 specification

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