AN3137 datasheet(10/42 Pages) STMICROELECTRONICS

10 / 42 page

STM8L/STM8AL ADC internal hardware

AN3137

10/42

Doc ID 16983 Rev 3

Figure 6.

Step 2: if MSB = 0, then compare with ¼ VREF

Compare with ¼ VREF; if MSB =0. S1 remained switched to ground. S2 switched to VREF.

1.2

ADC resolution

ADC resolution can be set in 4 steps: 6-bit, 8-bit, 10-bit or 12-bit resolution. Decreasing the

resolution speeds up the conversion time.

1.3

ADC clock, sampling time, speed

The ADC is driven by a clock derived from the MCU system clock through a divider. The

divider divides the master clock by a factor 1 or 2. The maximum ADC clock is 16 MHz and

the minimum is 320 kHz.

Each conversion step (which consists of switching the capacitor network, comparing results,

and storing them to a register bit, as described in Figure 4 to Figure 6) is performed in one

ADC clock cycle. Consequently, a 12-bit conversion takes 12 cycles. The sampling period

(Figure 2) has a programmable range from 4 to 384 clock cycles (charging input sampling

capacitors).

The shortest conversion time for a 12-bit resolution is 1 µs (4 sampling clocks + 12

approximation clocks on a 16 MHz ADC clock). It is possible to further reduce the

conversion time by decreasing the ADC resolution (to 6 or 8 or 10 bits).

Once enabled, the ADC analog peripheral needs a tWKUP stabilization time before starting

the conversion. Refer to the datasheet of your device to know the exact tWKUP value (usually

3 µs).

The user must implement this stabilization delay in the STM8L/STM8AL firmware.

AN3137 Scheda tecnica(PDF) 10 Page - STMicroelectronics