DocID024590 Rev 3

7/25

AN4296

Overview of STM32F303xB/C and STM32F358xC CCM RAM

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The write protection is enabled through the SYSCFG CCM SRAM protection register

(SYSCFG_RCR). This is a write '1' once mechanism, which means that once the write

protection is enabled on a given CCM RAM page by programming the corresponding bit to

‘1’, it can be cleared only through a system reset. For more details refer to the product

reference manual.

1.2.4

CCM RAM parity check

A parity check is implemented on STM32F303xB/C and STM32F358xC microcontrollers. It

is disabled by default and can be enabled by the user when needed through an option bit

(SRAM_PE bit). When this option bit is cleared, the parity check is enabled for the first

16 Kbytes of SRAM and for the 8-Kbyte CCM RAM.