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Overview of STM32F303xB/C and STM32F358xC CCM RAM

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1

Overview of STM32F303xB/C and STM32F358xC CCM

RAM

1.1

Purpose

The STM32F303xB/C and STM32F358xC CCM RAM is tightly coupled with the Cortex™

core. it is primarily intended to execute code at maximum system clock frequency (72 MHz)

without any wait state penalty. It thus allows to significantly decrease critical task execution

time, compared to code execution from Flash memory.

CCM RAM is typically used for real-time and computation intensive routines, such as:

•

Digital power conversion control loops (switch mode power supplies, lighting)

•

Field-oriented 3-phase motor control

•

Real-time DSP tasks

When code is located in CCM RAM and data stored in the regular SRAM, the Cortex-M4

core is in the optimum Harvard configuration. A dedicated zero-wait state memory is

connected to each of its I- and D-bus (refer to Figure 1: STM32F303xB/xC and

STM32F358xC system architecture) and can thus perform at 1.25DMIPS/MHz up to

72 MHz, with a deterministic performance of 90 DMIPS. This also guarantees a minimal

latency if interrupt service routines are placed in the CCM RAM.

Example

A benchmark between the STM32F103xx and STM32F303xx microcontrollers using

STMicroelectronics MC library V3.4 shows that in case of single motor control using 3 shunt

algorithm, the FOC total execution time for STM32F303xx is 16.97 µs compared to 21.3 µs

in STMF103xx (see note below); with FOC core and sensorless core loops running from

CCM RAM for STM32F303xx. This means that the STM32F303xx is 20.33 % faster than the

STM32F103xx thanks to the CCM RAM.

Note:

FOC routines are programmed in structured C, so the values provided above do not

represent the fastest possible execution both for STM32F103xx and STM32F303xx. In

addition, the execution time is also function of the compiler used and of its version.

When the CCM RAM is not used for code, it can hold data like an extra SRAM memory.

However it cannot be accessed through DMA. It is not recommended to place both code

and data together in the CCM, since the Cortex core will have to fetch code and data from

the same memory with the risk of collisions. The core would then be in the Von Neuman

configuration, and its performance would drop from 1.25DMIPS/MHz to below

1DMIPS/MHz.