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August 10, 2011

IDT 89HPES10T4G2 Data Sheet

As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure

3(a), the master and slave SMBuses are tied together and the PES10T4G2 acts both as a SMBus master as well as a SMBus slave on this bus. This

requires that the SMBus master or processor that has access to PES10T4G2 registers supports SMBus arbitration. In some systems, this SMBus

master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To

support these systems, the PES10T4G2 may be configured to operate in a split configuration as shown in Figure 3(b).

In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.

The PES10T4G2 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of

the serial EEPROM.

Figure 3 SMBus Interface Configuration Examples

Hot-Plug Interface

The PES10T4G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES10T4G2

utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-

tion, whenever the state of a Hot-Plug output needs to be modified, the PES10T4G2 generates an SMBus transaction to the I/O expander with the

new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN

input pin (alternate function of GPIO) of the PES10T4G2. In response to an I/O expander interrupt, the PES10T4G2 generates an SMBus transaction

to read the state of all of the Hot-Plug inputs from the I/O expander.

General Purpose Input/Output

The PES10T4G2 provides 9 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin

may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These

alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.

Processor

PES10T4G2

SSMBCLK

SSMBDAT

MSMBCLK

MSMBDAT

SMBus

Master

Other

SMBus

Devices

Serial

EEPROM

Processor

PES10T4G2

SSMBCLK

SSMBDAT

MSMBCLK

MSMBDAT

SMBus

Master

Other

SMBus

Devices

Serial

EEPROM

...

...

(a) Unified Configuration and Management Bus

(b) Split Configuration and Management Buses