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August 10, 2011

IDT 89HPES10T4G2 Data Sheet

Pin Description

The following tables list the functions of the pins provided on the PES10T4G2. Some of the functions listed may be multiplexed onto the same pin.

The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)

level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Note: In the PES10T4G2, the three downstream ports are labeled ports 2, 4, and 6.

Signal

Type

Name/Description

PE0RN[3:0]

PE0RP[3:0]

I

PCI Express Port 0 Serial Data Receive. Differential PCI Express receive

pairs for port 0. Port 0 is the upstream port.

PE0TN[3:0]

PE0TP[3:0]

O

PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 0. Port 0 is the upstream port.

PE2RN[1:0]

PE2RP[1:0]

I

PCI Express Port 2 Serial Data Receive. Differential PCI Express receive

pairs for port 2.

PE2TN[1:0]

PE2TP[1:0]

O

PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 2.

PE4RN[1:0]

PE4RP[1:0]

I

PCI Express Port 4 Serial Data Receive. Differential PCI Express receive

pairs for port 4.

PE4TN[1:0]

PE4TP[1:0]

O

PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 4.

PE6RN[1:0]

PE6RP[1:0]

I

PCI Express Port 6 Serial Data Receive. Differential PCI Express receive

pairs for port 6.

PE6TN[1:0]

PE6TP[1:0]

O

PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 6.

PEREFCLKP[0]

PEREFCLKN[0]

I

PCI Express Reference Clock. Differential reference clock pair input. This

clock is used as the reference clock by on-chip PLLs to generate the clocks

required for the system logic and on-chip SerDes. The frequency of the dif-

ferential reference clock is determined by the REFCLKM signal.

REFCLKM

I

PCI Express Reference Clock Mode Select. This signal selects the fre-

quency of the reference clock input.

0x0 - 100 MHz

0x1 - 125 MHz

This pin should be static and not change following the negation of

PERSTN.

Table 2 PCI Express Interface Pins

Signal

Type

Name/Description

MSMBADDR[4:1]

I

Master SMBus Address. These pins determine the SMBus address of the

serial EEPROM from which configuration information is loaded.

MSMBCLK

I/O

Master SMBus Clock. This bidirectional signal is used to synchronize

transfers on the master SMBus.

MSMBDAT

I/O

Master SMBus Data. This bidirectional signal is used for data on the mas-

ter SMBus.

Table 3 SMBus Interface Pins (Part 1 of 2)