ATmega16 datasheet(40/315 Pages) ATMEL

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ATmega16(L)

2466E–AVR–10/02

Watchdog Timer Control

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the ATmega16 and will always read as zero.

• Bit 4 – WDTOE: Watchdog Turn-off Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog

will not be disabled. Once written to one, hardware will clear this bit after four clock

cycles. Refer to the description of the WDE bit for a Watchdog disable procedure.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is

written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared

if the WDTOE bit has logic level one. To disable an enabled Watchdog Timer, the follow-

ing procedure must be followed:

In the same operation, write a logic one to WDTOE and WDE. A logic one must

be written to WDE even though it is set to one before the disable operation

starts.

Within the next four clock cycles, write a logic 0 to WDE. This disables the

Watchdog.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the

Watchdog Timer is enabled. The different prescaling values and their corresponding

Timeout Periods are shown in Table 17.

Bit

765

321

–

WDTOE

WDE

WDP2

WDP1

WDP0

WDTCR

Read/Write

R/W

Initial Value

Table 17. Watchdog Timer Prescale Select

WDP2

WDP1

WDP0

Number of WDT

Oscillator Cycles

Typical Time-out

at V

CC = 3.0V

Typical Time-out

at V

CC = 5.0V

16K (16,384)

17.1 ms

16.3 ms

32K (32,768)

34.3 ms

32.5 ms

64K (65,536)

68.5 ms

65 ms

128K (131,072)

0.14 s

0.13 s

256K (262,144)

0.27 s

0.26 s

512K (524,288)

0.55 s

0.52 s

1,024K (1,048,576)

1.1 s

1.0 s

2,048K (2,097,152)

2.2 s

2.1 s

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