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ADP2230ACPZ-R7 Scheda tecnica(PDF) 14 Page - Analog Devices |
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ADP2230ACPZ-R7 Scheda tecnica(HTML) 14 Page - Analog Devices |
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14 / 18 page ![]() ADP2230 Data Sheet Thermal Shutdown In the event that the junction temperature of the ADP2230 rises above 150°C, the thermal shutdown protection circuit turns off the regulator. Extreme junction temperature can be the result of high current operation, poor circuit board design, and/or high ambient temperature. A 15°C hysteresis is included in the protection circuit so that when a thermal shutdown occurs, the device does not return to normal operation until the on-chip temperature drops below 135°C. Upon exiting thermal shutdown, the soft start sequences are initiated. Soft Start The ADP2230 has an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. Typical soft start time is 350 μs. The ADP2230 is also capable of starting up into a precharged output capacitor. If soft start is invoked when the output capacitor charge is greater than zero, the device delays the start of switching until the internal soft start ramp reaches the corresponding FB voltage. This feature prevents discharging the output capacitor at the beginning of soft start. Current Limit The ADP2230 has protection circuitry that limits the direction and amount of current that flows through the power switch and synchronous rectifier, cycle by cycle. The positive current limit of 1300 mA ( typical) on the power switch limits the amount of current that can flow from the input to the output. In PWM, the ADP2230 also has a negative current limit of 500 mA (typical), on the synchronous rectifier that prevents the inductor current from reversing direction and flowing out of the load. 100% Duty Cycle The ADP2230 enters and exits 100% duty cycle smoothly. The control loop seeks the next clock cycle while the high-side switch is engaged. When this occurs, the clock signal is masked, and the PMOS remains on. When the input voltage increases, the internal VCOMP node decreases its signal to the control loop; thus, the device stops skipping clock cycles and exits 100% duty cycle. Rev. A | Page 14 of 18 |
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