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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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MB91F585LC Scheda tecnica(PDF) 5 Page - SPANSION |
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MB91F585LC Scheda tecnica(HTML) 5 Page - SPANSION |
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5 / 177 page  D at aS h ee t 2 MB91F587LA_DS705-00012-2v0-E, August 22, 2014 CONFIDENTIAL • Interrupt (PC/PS saving) 6 cycles (16 priority levels) • The Harvard architecture allows simultaneous execution of program and data access. • Instruction compatibility with the FR family • Built-in memory protection function (MPU) • Eight protection areas can be specified commonly for instructions and data. • Control access privilege in both privilege mode and user mode • Built-in FPU (floating-point operation) • IEEE754 compliant • Floating-point register: 32 bits × 16 sets • Peripheral Functions • Clock generation (SSCG function is available) • Main oscillation (4 to 20 MHz) • PLL multiplication rate:1 to 32 times • CR oscillation • Oscillation frequency: 100kHz, with frequency accuracy ± 50% (pre-trimming) • Trimming is enabled • To be used as a count clock of hardware watchdog • MB91F585LC/F586LC/F587LC/F585LD/F586LD/F587LD: Oscillation stop feature during stand-by is not available • MB91F585LA/F586LA/F587LA/F585LB/F586LB/F587LB: Oscillation stop feature during stand-by is available • Built-in program flash memory capacity MB91F585L: 512+64 Kbytes MB91F586L: 768+64 Kbytes MB91F587L: 1024+64 Kbytes • Built-in data flash (WorkFlash) 64 Kbytes • Built-in RAM capacity • Main RAM MB91F585L: 48 Kbytes MB91F586L: 64 Kbytes MB91F587L: 96 Kbytes • Backup RAM 8 Kbytes • General-purpose ports: MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC 98 ports MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD 111 ports • Including eight I2C pseudo open drain corresponding ports • External bus interface (MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD) • Maximum operating frequency: 40MHz • 22-bit address, 16-bit data • DMA controller • Up to 8 channels can be started simultaneously. • 2 transfer factors (Internal peripheral request and software) • External interrupt input: 8 channels Level ("H" / "L") or edge detection (rising or falling) enabled • Multi-function serial communication (built-in transmission/reception FIFO memory): 5 channels < UART (Asynchronous serial interface) > • Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO memory • Parity or no parity is selectable. • Built-in dedicated baud rate generator • An external clock can be used as the transfer clock • Parity, frame, and overrun error detection functions provided • DMA transfer supported |
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