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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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MB91F585LC Scheda tecnica(PDF) 6 Page - SPANSION |
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MB91F585LC Scheda tecnica(HTML) 6 Page - SPANSION |
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6 / 177 page  D at aS h ee t August 22, 2014, MB91F587LA_DS705-00012-2v0-E 3 CONFIDENTIAL <CSIO (Synchronous serial interface) > • Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO memory • SPI supported; master and slave systems supported; 5 to 16, 20, 24, 32-bit data length can be set. • Built-in dedicated baud rate generator (Master operation) • An external clock can be entered. (Slave operation) • Overrun error detection function is provided. • Built-in chip selection function • DMA transfer supported <LIN interface (v2.1)> • Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO memory • LIN protocol revision2.1 supported. • Master and slave systems supported • Framing error and overrun error detection • LIN synch break generation and detection; LIN synch delimiter generation • Built-in dedicated baud rate generator • An external clock can be adjusted by the reload counter. • DMA transfer supported < I2C > • Supported for 4 channels: ch.0,ch.1,ch.3, and ch4. • Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO memory • Standard mode (Max. 100 kbps) / high-speed mode (Max. 400 kbps) supported • DMA transfer supported (for transmission only) • CAN controller (CAN): 3 channels • Transfer speed: Up to 1Mbps • 64-transmission/reception message buffering: 3 channels • FlexRay controller: 1unit(ch.A/ch.B) • FlexRay Specifications Version 2.1 supported • Up to 128 message buffers • 8K bytes of message RAM • Variable length of message buffers • Each message buffer can be allocated as a part of reception buffer, transmission buffer or reception FIFO memory • Host access to the message buffer via input and output buffers • Filtering for slot counter, cycle counter and channels • Maskable interrupts are supported • PPG: 16 bits × 24 channels • Reload timer: 16 bits × 4 channels • A/D converter (successive approximation type) • 12-bit resolution: 3units(24 channels) • Conversion time: 1 µs • Free-run timer: 16 bits × 6 channels (1 channel can be selected for input capture, and 1 channel for output compare.) • Input capture: 16 bits × 8 channels (linked to the free-run timer) • Output compare: 16 bits × 12 channels (linked to the free-run timer) • Waveform generator: 2 units (12 channels) • R/D converter: 1 channel (MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC) • 10-bit D/A converter: 1 channel (MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD) • Calibration: The hardware watchdog for CR oscillation drive The CR oscillation frequency can be trimmed. |
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