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LM25101A, LM25101B, LM25101C

www.ti.com

SNVS859B – JULY 2012 – REVISED APRIL 2013

TIMING DIAGRAM

Figure 20.

Layout Considerations

The optimum performance of high and low-side gate drivers cannot be achieved without taking due

considerations during circuit board layout. Following points are emphasized.

1. Low ESR / ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the

HB and HS pins to support the high peak currents being drawn from VDD during turn-on of the external

MOSFET.

2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be

connected between MOSFET drain and ground (VSS).

3. In order to avoid large negative transients on the switch node (HS pin), the parasitic inductances in the

source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.

4. Grounding Considerations:

(a) The first priority in designing grounding connections is to confine the high peak currents that charge and

discharge the MOSFET gate into a minimal physical area. This will decrease the loop inductance and

minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as

possible to the gate driver.

(b)

The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground

referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on

a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.

The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length

and area on the circuit board is important to ensure reliable operation.

A recommended layout pattern for the driver is shown in Figure 21. If possible a single layer placement is

preferred.

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