0.1

1.0

10.0

100.0

1000.0

SWITCHING FREQUENCY (kHz)

0.001

0.010

0.100

1.000

To Hi-Side FET

To Low-Side FET

Single Layer

Option

Multi Layer

Option

Recommended Layout for Driver IC and

Passives

VSS

LO

LI

SO

Power

Pad-8

HI

VDD

HB

HO

HS

LM25101A, LM25101B, LM25101C

SNVS859B – JULY 2012 – REVISED APRIL 2013

www.ti.com

Figure 21. Recommended Layout Pattern

Power Dissipation Considerations

The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate

voltage (VDD) and can be roughly calculated as:

2

(1)

There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and

HO outputs. Figure 22 shows the measured gate driver power dissipation versus frequency and load

capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the

power losses driving the output loads and agrees well with Equation 1. This plot can be used to approximate the

power losses due to the gate drivers.

Figure 22. Gate Driver Power Dissipation (LO + HO)

12

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