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DSC2011

Page 2

MK-Q-B-P-D-12042602-2

DSC2011

Low-Jitter Configurable Dual CMOS Oscillator

Pin Description

Pin No. Pin Name Pin Type

Description

1

Enable

I

Enables outputs when high and disables when low

2

NC

NA

Leave unconnected or grounded

3

O2S0

I

Least significant bit for drive strength selection for Output 2

4

GND

Power

Ground

5

FS0

I

Least significant bit for frequency selection

6

FS1

I

Middle bit for frequency selection

7

FS2

I

Most significant bit for frequency selection

8

Output1

O

CMOS output 1

9

O1S0

I

Least significant bit for drive strength selection for output 1

10

O1S1

I

Most significant bit for drive strength selection for output 1

11

Output2

O

CMOS output 2

12

VDD2

Power

Power Supply for Output 2

13

VDD

Power

Power Supply

14

O2S1

I

Most significant bit for drive strength selection for output 2

Operational Description

The DSC2011 is a dual output CMOS oscillator

consisting of a MEMS resonator and a support

PLL IC. The two CMOS outputs are generated

through

independent

8-bit

programmable

dividers from the output of the internal PLL.

For temp ranges up to Industrial, two

constraints

are

imposed

on

the

output

are even integers between 4 and 254, 2)

factory for acceptable frequency combinations

for other temp ranges.

The actual frequencies output by the DSC2011

are controlled by an internal pre-programmed

memory (OTP).

This memory stores all

coefficients required by the PLL for up to eight

different frequency combinations.

Three

control pins (FS0 – FS2) select the output

frequency combination.

Discera supports

customer defined versions of the DSC2011.

Standard frequency options are described in in

the following sections.

The DSC2011 has independent control of the

output voltage levels of the two outputs. The

high voltage level of Output 1 is equal to the

main supply voltage, VDD (pin 13).

VDD2

(pin 12) sets the high voltage level of Output

2. VDD2 must be equal to or less than VDD at

all times to insure proper operation.

VDD2

can be as low as 1.65V.

When Enable (pin 1) is floated or connected to

VDD, the DSC2011 is in operational mode.

Driving Enable to ground will tri-state both

output drivers (hi-impedance mode).

The DSC2011 has programmable output drive

strength for each output. Using two control

pins (OXS0-OXS1) for each output, the drive

strength can be independently adjusted to

match circuit board impedances to reduce

power supply noise, overshoot/undershoot

and EMI. Table 1 displays typical rise / fall

times for the output with a 15pf load

capacitance as a function of these control pins

at VDD=3.3V and room temperature.

Table 1. Rise/Fall times for drive strengths

Output Drive Strength Bits

[OXS1, OXS0] - Default [11]

00

01

10

11

1.6

1.4

1.2

1.1

2.4

2.2

1.5

1.4