LP8501 datasheet(34/51 Pages) TI1

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LP8501

SNVS548D – SEPTEMBER 2008 – REVISED AUGUST 2013

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Table 5. Control Register Map (continued)

Hex

Bit(s)

Read/Wr

Default Value

Bit Mnemonic and Description

Address

ite

After Reset

GPO

[2]

R/W

xxxxx0xx

INT_CONF

INT pin can be configured to function as a GPO with

this bit.

[1]

R/W

xxxxxx0x

GPO

GPO pin control

[0]

R/W

xxxxxxx0

INT_GPO

GPO pin control for INT pin (when INT_CONF is set

to '1')

RESET

[7:0]

R/W

00000000

RESET

Writing 11111111 into this register resets the LP8501

LED TEST CONTROL

[7]

R/W

0xxxxxxx

EN_LED_TEST_ADC

[6]

R/W

x0xxxxxx

EN_LED_TEST_INT

[5]

R/W

xx0xxxxx

LED_TEST_CONTINUOUS_CONV

Continuous LED test measurement selection

[4:0]

R/W

xxx00000

LED_TEST_CTRL

Control bits for LED test

LED TEST ADC

[7:0]

N/A

LED_TEST_ADC

LED test result

GROUP FADER1

[7:0]

R/W

00000000

GROUP FADER

GROUP FADER2

[7:0]

R/W

00000000

GROUP FADER

GROUP FADER3

[7:0]

R/W

00000000

GROUP FADER

ENG1 PROG START

[6:0]

R/W

x0000000

ADDR

ENG2 PROG START

[6:0]

R/W

x0001000

ADDR

ENG3 PROG START

[6:0]

R/W

x0010000

ADDR

PROG MEM PAGE SEL

[2:0]

R/W

xxxxx000

PAGE_SEL

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