LP8501 datasheet(39/51 Pages) TI1

39 / 51 page

LP8501

www.ti.com

SNVS548D – SEPTEMBER 2008 – REVISED AUGUST 2013

27 D2 CURRENT CONTROL to 2E D9 CURRENT CONTROL

•

The control registers and control bits for D2 output up to D9 output are similar to that given to D1 output.

36 CONFIG

•

This register contains miscellaneous control bits.

•

36 — Bit [7] PWM_POWERSAVE

–

1 = PWM powersave ON

–

0 = PWM powersave OFF

–

See the Power Saving section for further details.

•

36 — Bit [6] EN_AUTO_INCR

–

The automatic increment feature of the serial bus address enables a quick memory write of successive

registers within one transmission.

–

1 = serial bus address automatic increment is enabled.

–

0 = serial bus address automatic increment is disabled.

•

36 — Bit [5] POWERSAVE_EN

–

1 = power save mode is enabled.

–

0 = power save mode is disabled. See the Power Saving section for further details.

•

36 — Bits [4:3] CP_MODE

–

Charge pump operation mode

–

00 = OFF

–

01 = forced to bypass mode (1x)

–

10 = forced to 1.5x mode; output voltage is boosted to 4.5V.

–

11 = automatic mode selection

•

36 — Bit [2] FADE_TO_OFF

–

Enables group fading when device is shut down through CHIP_EN.

–

1 = Group fading ON.

–

0 = Group fading OFF.

•

36 — Bit [1] RESERVED

–

This bit is reserved and should be written to zero.

•

36 — Bits [0] Clock selection bit

–

Program execution is clocked with internal 32 kHz clock or with external clock. Clocking is controlled with

bits [1:0] n the following way:

–

0 = external clock source (CLK pin)

–

1 = internal clock

–

External clock can be used if a clock signal is present on CLK-pin. External clock frequency must be 32

kHz for correct operation. If a higher or a lower frequency is used, it will affect on the program engine

operation speed.

–

If external clock is not used in the application, CLK pin should be connected to GND to avoid oscillation on

this pin and extra current consumption.

37 ENGINE1 PC

•

37 — Bits [6:0] PC

–

Program counter starting value for program execution engine 1; A value from 0000000 to 1100000. The

maximum value depends on program memory allocation between the three program execution engines.

38 ENGINE2 PC

•

38 — Bits [6:0] PC

–

Program counter starting value for program execution engine 2; A value from 0000000 to 1100000.

39 ENGINE3 PC

•

39 — Bits [6:0] PC

–

Program counter starting value for program execution engine 3; A value from 0000000 to 1100000.

3A STATUS/INTERRUPT

Submit Documentation Feedback

Product Folder Links: LP8501

LP8501 Scheda tecnica(PDF) 39 Page - Texas Instruments

LP8501 Scheda tecnica(HTML) 39 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Scheda tecnica Scarica

Link URL