DS3875 datasheet(5/58 Pages) NSC

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Pin Definition (Continued)

of Pins

Type

Description

SIGNALS TOFROM THE HOST

(CPU Plus External Interface Logic)

DATA(70)

Data bus for the host to access the register bank of the controller

ADD(30)

Address bits for the register bank of the controller

CHIP SELECT

The host can read or write tofrom the controller

Readwrite signal from the host

DSACK

Data acknowledge pin for host readwrite

SEL

SELECT

Determines how the controller latches in data A ‘‘1’’ on the pin uses the rising

edge of CS

A ‘‘0’’ on the pin uses the falling edge of DSACK

MGRQ

MESSAGE REQUEST

Indicates to the controller to send an arbitration message

MGTX

MESSAGE TRANSMIT

Indicates the successful transmission of an arbitration message

ERINT

ERROR INTERRUPT

Indicates that an error occurred during the arbitration cycle

MGINT

MESSAGE INTERRUPT

Indicates the reception of an arbitration message

PFINT

POWER FAIL INTERRUPT

Indicates that a powerfail message was received

EXTERNAL LOGIC

IBA

CMPT

Signal to indicate that the Parallel Protocol controller may assert its bit on the ADDRESS

DATA bus if it is participating in an Idle Bus Arbitration

IBA

This signal indicates that IBA was successful If this module was a competitor in the IBA

competition (BRQ ) then this module is the winner and now the bus master If this module

was the master but did not compete in the IBA competition and IBA was successful then the

M bit (Status register) is negated

CANCEL

Indicates the start of the disconnection phase of the current master or cancel the current

arbitration cycle

LKD

LOCKED

Signal to indicate that resources have been locked in the current tenure and

hence generate either a dummy cycle if current master or UNLK otherwise (Decoded from

Futurebusa Command port output from Data Path Unit)

UNLK

UNLOCK

Transfer of tenure indication to the parallel protocol controller for unlocking its

resources Generated only if the LKD signal is asserted (To external logic)

FSTR

FIFO STROBE

Signal generated to load an external FIFO for received arbitration messages

CLK

Clock input to the internal PLL

External capacitor input for PLL01 mF

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