DS3875 datasheet(21/58 Pages) NSC

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50 Arbitrating for Futurebusa (Continued)

MGRQ will be given a higher priority and will be acted

upon during this arbitration cycle

BRQ will wait to arbi-

trate during the next arbitration cycle

5 A Bus Request ( BRQ ) will cause APO to be asserted

(if it is doing Single Pass or the First Pass of Two-Pass

Arbitration) This will cause the Futurebusa AP to be

asserted and will indicate to the other modules that an

arbitration competition is beginning

Note that the user will violate the Futurebusa specification

if he leaves the local modules resources locked ( LKD )

and has IBA enabled in the arbitration controller This inci-

dent is dangerous because it could lead to another module

winning IBA with the local modules resources being locked

If the other module tried to access the local modules re-

sources it would result in deadlock

5512 Phase 0 Idle Bus Arbitration Events That Cause

a Transition to Phase 1

If IBA is desired and the arbitration cycle is in Phase 0

( APO

AQI ARO) the parallel bus is idle (AS

AI )

and DS has been released for a minimum period of time

(Futurebusa spec) the Masters external logic may assert

This will alert any module capable of doing IBA that

IBA has been enabled

5513 Phase 0 Parking

The aim of Parking is to give the Futurebusa bus master

quick access to the bus to perform other transfers when no

one else desires to use it If Parking is enabled ( IBA

PK )

and is successful the arbitration controller will issue BGNT

in Phase 0 If another module gets a message request or

bus request the arbitration competition cycle begins like it

normally does to handle the request (see Section 554 for

more information)

552 Phase 1 Decision Phase

This Phase is characterized by AP and AR asserted and

released on Futurebusa

See

Figure 7b for the

DS3875 Arbitration Controller Phase 1 state diagram

The arbitration controller will be asserting APO and ARO

and negating AQO This is the state of the arbitration syn-

chronization lines when the decision phase (1) is in prog-

ress

During Phase 1 the individual modules must make the deci-

sion whether they want to compete This decision will be

based upon the state of the modules bus request message

request or locked status ( BRQ or MSGRQ or LKD )at

the time APO is asserted Since this condition is subject to

mestastability a metastable hardened latch is used internal

to the DS3875 to resolve this potential condition

If the module is going to compete the arbitration competition

number (CN(70)) and its parity bit (CNp) will be asserted to

the arbitration transceiver Latch enable of the arbitration

transceiver will be asserted and negated ( CN

LE assert-

ed for 20 ns) to latch in the arbitration number and compete

will be asserted ( CMPT ) to enable the arbitration competi-

tion number onto Futurebusa

If the module is a slow module ( FS

see Section 76) the

arbitration handshake signal AC0O will be asserted

Once the decision to compete has been made the arbitra-

tion handshake signal ( AC1O) that cancels the arbitration

cycle will be negated The Programmable Skew (PS(10))

gives time for the arbitration number to become valid on

Futurebusa before ARO is negated Once the Programma-

ble Skew has timed out ARO will be negated Once all mod-

ules have negated AR the arbitration cycle will transition to

Phase 2

Once all modules have negated AR a1 ms timer is started

This timer is used to guarantee that the competition cycle

does not get stuck in phase 2 During Phase 2 the winner of

the competition cycle after waiting its tA (arbitration settling

time) time transitions the cycle to Phase 3 The timer is

used to prevent livelock where the winning module may not

transition the cycle to Phase 3

5521 Phase 1 Idle Bus Arbitration Events That Cause

a Transition to Phase 2

During phase 1 the arbitration controller will output

IBA

CPT

When the external logic sees

IBA

CTP and the

parallel bus is inactive (AS

AI ) it should drive one

of the data bits of the parallel addressdata bus

553 Phase 2 Competition Phase

This Phase is characterized by AP asserted and AQ and

released on Futurebusa

See

Figure 7c for the

DS3875 Arbitration Controller Phase 2 state diagram

The arbitration controller will be asserting APO negating

AQO and receiving ARI negated This is the state of the

arbitration synchronization lines when the competition

phase (2) is in progress

While in Phase 2 the following actions are performed

1 AB

RE is asserted after 30 ns This allows the arbitra-

tion controller to monitor the winning competition num-

ber

2 The FIFO STRobe is now asserted ( FSTR )

There are two conditions that can cause AQO to be assert-

ed causing a transition to Phase 3

1 The AQI input being asserted

2 Competing arbitration competition settling time (ta) ex-

pired one ms Phase 2 arbitration error timer not expired

and the WIN

GT input being asserted

5531 Phase 2 Idle Bus Arbitration Events That Cause

a Transition to Phase 3

The external logic should drive the IBA Success signal

( IBA

S ) during phase 2 if DI is released only this mod-

ules data bit is driven on the data bus and the arbitration

settling Time (ts) has not expired

When the arbitration controller sees

IBA

S asserted it

will issue bus grant ( BGRNT ) to give access of the bus to

the module that won the IBA If two or more modules have a

request then normal arbitration will determine which mod-

ule will gain access

554 Phase 3 Error Check Phase

This Phase is characterized by AP and AQ asserted AR

released on Futurebusa See

Figure 7d for the DS3875

Arbitration Controller Phase 3 state diagram Also see

Fig-

ures 6b c d for how AS

CANCEL relates to Phase 3

The arbitration controller will be asserting APO and AQO

and negating ARO This is the state of the arbitration syn-

chronization lines when the error check phase (3) is in prog-

ress

While in Phase 3 the following actions are performed

1 If the module is a competitor and winner of the arbitra-

tion the W(winner) bit in the STATUS register is set

2 Upon entering phase 3 after 20 ns AB

RE is negated

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