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TMS320C6472ECTZ Scheda tecnica(PDF) 46 Page - Texas Instruments |
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TMS320C6472ECTZ Scheda tecnica(HTML) 46 Page - Texas Instruments |
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46 / 269 page ![]() TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL TYPE(1) IPD/IPU(2) (3) DESCRIPTION NAME NO. 1.8-V DDR PLL analog supply voltage NC or connected to VSS, if DDR is not used NOTE: If the DDR2 Memory Controller is not used, the DVDD18, DVDD18MON, VREFSSTL, AVDDA3, AVDDA4, CVDD1, PTV18P, and AVDDA3 B21 I PTV18N pins can be NC or connected directly to VSS (GND) to save power. However, connecting these pins this way prevents boundary scan from functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2 Memory Controller pins, see Section 7.3.3. H4 1.8-V DDR analog supply voltage NC or connected to VSS, if DDR is not used NOTE: If the DDR2 Memory Controller is not used, the DVDD18, DVDD18MON, VREFSSTL, AVDDA3, AVDDA4, CVDD1, PTV18P, and AVDDA4 I PTV18N pins can be NC or connected directly to VSS (GND) to A21 save power. However, connecting these pins this way prevents boundary scan from functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2 Memory Controller pins, see Section 7.3.3. T23 1.2-V RapidIO digital supply voltage NC or connected to VSS, if RapidIO is not used Do not connect this SERDES supply to CVDD1 NOTE: If the RapidIO interface is not used, the CVDD2, AVDDA, DVDDD I DVDDD, DVDDR, and AVDDT pins can be NC or connected directly V23 to VSS (GND) to reduce power use. However, connecting these pins in this way prevents boundary scan from functioning on the RapidIO pins. To preserve boundary-scan functionality on the RapidIO pins, see Section 7.3.3. 1.5-V/1.8-V RapidIO regulator supply voltage NC or connected to VSS, if RapidIO is not used NOTE: If the RapidIO interface is not used, the CVDD2, AVDDA, DVDDD, DVDDR, and AVDDT pins can be NC or connected directly DVDDR R28 I to VSS (GND) to reduce power use. However, connecting these pins in this way prevents boundary scan from functioning on the RapidIO pins. To preserve boundary-scan functionality on the RapidIO pins, see Section 7.3.3. A1 A19 B10 B14 B5 E1 E12 E16 1.8-V I/O supply voltage for DDR2 buffers NC or connected to VSS, if DDR is not used E6 NOTE: If the DDR2 Memory Controller is not used, the DVDD18, F15 DVDD18MON, VREFSSTL, AVDDA3, AVDDA4, CVDD1, PTV18P, and DVDD18 F17 I PTV18N pins can be NC or connected directly to VSS (GND) to save power. However, connecting these pins this way prevents F19 boundary scan from functioning on the DDR2 Memory Controller G10 pins. To preserve boundary-scan functionality on the DDR2 Memory Controller pins, see Section 7.3.3. G12 G14 G16 G18 G6 G8 H7 J6 46 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TMS320C6472 |
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