TMS320C6472ECTZ datasheet(7/269 Pages) TI1

7 / 269 page

TMS320C6472

www.ti.com

SPRS612G

– JUNE 2009 – REVISED JULY 2011

Device Overview

NOTE

Unless otherwise noted, all address locations in this document are stated in hexidecimal

numbers.

2.1

Device Characteristics

Table 2-1, provides an overview of the C6472 DSP. The table shows significant features of the C6472

device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type

with pin count.

Table 2-1. Characteristics of the C6472 Processor

HARDWARE FEATURES

C6472

DDR2 Memory Controller (32-bit bus width) [1.8 V I/O]

(clock source = CLKIN3)

EDMA (64 independent channels)

High-speed Serial RapidIO Port

I2C

Peripherals

HPI (16 bit)

Not all peripheral pins are

Telecom Serial Interface Port (TSIP)

available at the same time

(for more detail, see

UTOPIA (16/8-bit mode, 50-MHz, slave-only)

Section 3).

10/100/1000 Mb/s Ethernet MAC (EMAC)

Management Data Input/Output (MDIO)

12 (6 dedicated [0-5], 1 per core; 6 shared [6-11])

64-bit Timers (Configurable)

1 64-bit or 2 32-bit or WD each

General-Purpose Input/Output Port (GPIO)

32K-Byte L1 Program Memory [SRAM/Cache]

Organization per C64x+ Megamodule

32K-Byte L1 Data Memory [SRAM/Cache]

608K-Byte L2 Unified Memory [SRAM/Cache]

On-Chip Memory

768K-byte SL2 Unified SRAM

Shared by all 6 C64x+ Megamodules

768K-byte SL2 ROM

CPU MegaModule

Revision ID Register (MM_REVID.[15:0])

0003h

Revision ID

Address 0181 2000

JTAG ID register

JTAG ID

0009 102Fh

Address 02A8 0008

Frequency

MHz

500/625/700 MHz

Cycle Time

2 ns/1.6 ns

1.2 V (DDR2 EMIF)

Core (V)

1.0 V (500 MHz) / 1.1 V (625 MHz) / 1.2 V (700 MHz)

1.2 V [RapidIO],

Voltage

1.5 V/1.8 V [EMAC RGMII],

I/O (V)

1.8 V [DDR2 EMIF I/O], and

1.8 V and 3.3 V [I/O Supply Voltage]

PLL1 and

CLKIN frequency multiplier

Bypass (x1), x10-x32

PLL1 Controller Options

PLL2 and

CLKIN frequency multiplier

x20

PLL2 Controller Options

[EMAC support]

PLL3 and

CLKIN frequency multiplier

x20

PLL3 Controller Options

[DDR2 Memory Controller support only]

BGA Package

24 x 24 mm

737-Pin Flip-Chip Plastic BGA (CTZ/ZTZ)

Process Technology

μm

0.09

μm

Device Overview

Submit Documentation Feedback

Product Folder Link(s) :TMS320C6472

TMS320C6472ECTZ Scheda tecnica(PDF) 7 Page - Texas Instruments

TMS320C6472ECTZ Scheda tecnica(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL