FEDL7066-01

ML7066

21/29

When SCLK is a negative clock

(Notes)

The SINT pin signal occurs at the timing independent of the signals of other clock synchronous

serial interface related pins.

The above diagrams show the case of input/output from the MSB. It can be changed to

input/output from the LSB through the MODE pin setting.

**: Although the output value is not specified, MSB data is output in the case of input/output from

the MSB indicated above.

For input/output from the LSB, LSB data is output.

SCEN

SCLK

SDO

SDIN

MSB IN

BITS6-1

LSB IN

MSB OUT

BITS6-1

LSB OUT

(**)

SCEN