ML7066 datasheet(22/29 Pages) LAPIS

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FEDL7066-01

ML7066

22/29

Transmit/Receive Data Interface Characteristics

(Operation power supply voltage: 2.1V - 3.6V, Ta=-25 - +65°C)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

DIO input setup time

TDISU

At transmission

—

DIO input hold time

TDIH

At transmission

—

DCLK output delay time

TDCKOD

At reception

—

DIO output hold time

TDOH

At reception

Load

capacitance

CL= 50pF

—

(Notes)

All the timings are measured at the 20% and 80% levels of VDDIO.

The DCLK clock frequency FDCLK is 600Hz / 1200Hz / 2400Hz / 4800Hz.

Reset Characteristics

(Operation power supply voltage: 2.1V - 3.6V, Ta=—25 - +65°C)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

RESETN delay time (at power on)

TRDL

After all power supply pins

are powered on

—

SRESETN pulse time

TRPLS

RESETN=1

200

—

SRESETN delay time (when operating)

TRDOP

—

RESETN-SRESETN setup time

(when operating)

TRSU

—

(Notes)

All the timings are measured at the 20% and 80% levels of VDDIO.

VDD

VDD voltage

level

GND level

RESETN

SRESETN

TRDO

TRDL

TRPL

TRSU

DCL

DIO

(At

reception)

DIO

(At

transmission)

VALID

TDCKOD

TDOH

FDCLK

TDIS

TDI

VALID

TDCKOD

FDCLK

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