CS89712 datasheet(126/170 Pages) CIRRUS

Il numero della parte	CS89712

Spiegazioni elettronici	HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER

PDF	170 Pages

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Produttore elettronici	CIRRUS [Cirrus Logic]

Homepage	http://www.cirrus.com

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CS89712

126

DS502PP2

3.18.11 Transmit Collision Counter (TxCOL, address offset 132h)

The TxCOL counter (Bits 6 through F) is incremented whenever the 10BASE-T Receive Pair (RXD+ / RXD-) be-

comes active while a packet is being transmitted. If the TxColOvfiE bit (Register B, BufCFG, Bit C) is set, there is an

interrupt when TxCOL increments from 1FFh to 200h. This interrupt provides the software with an early warning that

the TxCOL counter should be read before it reaches 3FFh and starts over (by interrupting at 200h, the software has

an additional 512 counts before TxCOL actually overflows). The TxCOL counter is cleared when read.

Reset value is: 0000 0000 0001 0010

7:6

5:0

F:8

ColCount

010010

ColCount

Bit

Description

5:0

010010: These bits provide an internal address used by the CS89712 to identify this as register

12, the Transmit Collision Counter. When reading this register, these bits will be 010010, where

the LSB corresponds to Bit 0.

7:6

F:8

ColCount: The upper ten bits contain the number of collisions.

Table 76. Transmit Collision Counter

CS89712 Scheda tecnica(PDF) 126 Page - Cirrus Logic