CS89712 datasheet(41/170 Pages) CIRRUS

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CS89712

DS502PP2

pixels is mapped to a set of consecutive bytes or

words in the video RAM. The video frame buffer

can be accessed word wide as pixel 0 is mapped to

the LSB in the buffer such that the pixels are ar-

ranged in a little endian manner.

The pixel bit rate, and hence the LCD refresh rate,

can be programmed from 18.432 MHz to 576 kHz.

The LCD controller is programmed by writing to

the LCD control register (LCDCON). The LCD-

CON register should not be reprogrammed while

the LCD controller is enabled.

The LCD controller also contains two 32-bit palette

registers, which allow any 4-, 2-, or 1-bit pixel val-

ue to be mapped to any of the 15 grayscale values

available. The palette registers are bypassed in

Snooze State.

The required DMA bandwidth to support a ½ VGA

panel displaying 4 bits-per-pixel data at an 80 Hz

refresh rate is approximately 6.2 Mbytes/sec. As-

suming the frame buffer is stored in a 32-bit wide

the maximum theoretical bandwidth available is

86 Mbytes/sec at 36.864 MHz.

The LCD controller uses a nine stage 32-bit wide

FIFO to buffer display data. The LCD controller re-

quests new data when there are five words remain-

ing in the FIFO. This means that for a ½ VGA

display at 4 bits-per-pixel and 80 Hz refresh rate,

the maximum allowable DMA latency is approxi-

mately 3.25

µsec ((5 words x 8 bits/byte) / (640 x

240 x 4 bpp x 80 Hz)) = 3.25

µsec). The worst-case

latency is the total number of cycles from when the

DMA request appears to when the first DMA data

word actually becomes available at the FIFO.

DMA has the highest priority, so it will always hap-

pen next in the system. The maximum number of

cycles required is 36 from the point at which the

DMA request occurs to the point at which the STM

is complete, then another 6 cycles before the data

actually arrives at the FIFO from the first DMA

read. This creates a total of 42 cycles assuming the

frame buffer is located in 32-bit wide memory.

With 16-bit wide memory, the worst-case latency

will double. In this case, the maximum permissible

display size may be halved, to approximately 320 x

240 pixels, depending on required pixel depth and

refresh rate. If 18 MHz mode is selected with 32-bit

wide memory, then the worst-case latency will be

2.26

µsec (i.e., 42 cycles x 54 nsec/cycle). If

36 MHz mode is selected, and 32-bit wide, then the

worst-case latency drops down to 1.49

µs. If the

frame buffer is to be stored in static memory, then

further calculations must be performed. This calcu-

lation is a little more complex for 36 MHz mode of

operation. The total number of cycles = (12 x 4) +

7 = 55. Thus, 55 x 27 ns = ~1.49

µsec.

Figure 11 shows the organization of the video map

for all combinations of bits-per-pixel.

The refresh rate is not affected by the number of

bits-per-pixel; however the LCD controller fetches

twice the data per refresh for 4 bits-per-pixel com-

pared to 2 bits-per-pixel. The main reason for re-

ducing the number of bits-per-pixel is to reduce the

power consumption of the memory where the video

frame buffer is mapped.

2.19 Timer Counters

Two identical timer counters are integrated into the

CS89712. These are referred to as TC1 and TC2.

Each timer counter has an associated 16-bit read /

write data register and some control bits in the sys-

tem control register. Each counter is loaded with

the value written to the data register immediately.

This value will then be decremented on the second

active clock edge to arrive after the write (i.e., after

the first complete period of the clock). When the

timer counter under flows (i.e., reaches 0), it will

assert its appropriate interrupt. The timer counters

can be read at any time. The clock source and mode

are selectable by writing to bits in the system con-

trol register. 512 kHz and 2 kHz rates are provided.

The timer counters can operate in two modes: free

running or pre-scale.

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