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8P34S2108NLGI Scheda tecnica(PDF) 13 Page - Integrated Device Technology

Il numero della parte 8P34S2108NLGI
Spiegazioni elettronici  Dual 1:8 LVDS Output 1.8V Fanout Buffer
PDF  20 Pages
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Produttore elettronici  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
Logo IDT - Integrated Device Technology

8P34S2108NLGI Scheda tecnica(HTML) 13 Page - Integrated Device Technology

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©2016 Integrated Device Technology, Inc.
October 20, 2016
8P34S2108 Datasheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value
should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100
parallel resistor at the receiver and a 100
 differential transmission-line environment. In order to avoid any transmission-line reflection
issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS
compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown
in Figure 7 can be used with either type of output structure. Figure 8, which can also be used with both output types, is an optional
termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a
non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In
addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for
compatibility with the output.
Figure 7. Standard LVDS Termination
Figure 8. Optional LVDS Termination
LVDS
Driver
ZO  ZT
ZT
LVDS
Receiver
LVDS
Driver
ZO  ZT
LVDS
Receiver
C
ZT
2
ZT
2



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