UT80C196 datasheet(13/42 Pages) AEROFLEX

13 / 42 page

Legend for I/O fields:

= TTL compatible output

= TTL compatible input

= CMOS only input

TUO

= TTL compatible output

(internally pulled high)

TDO

= TTL compatible output

(internally pulled low)

TUI

= TTL compatible input

(internally pulled high)

TDI

= TTL compatible input

(internally pulled low)

= TTL compatible bidirectional

TUQ

= TTL compatible quasi-bidirectional

(internally pulled high)

TUB

= TTL compatible bidirectional

(internally pulled high)

TUBS

= TTL compatible bidirectional Schmitt

Trigger (internally pulled high)

PWR

= +5V (VDD)

GND

= OV (VSS)

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

PWR

VDD

---

Digital supply voltage (+5V). There are 2 VDD pins, both of

which must be connected.

ECB51

---

EDAC Check Bit 5. Asserting the EDACEN pin will cause the

error detection and correction engine to pass the EDAC Check

Bit 5 through pin 2 of the UT80C196KD.

TDI

NMI

High

Non-Maskable Interrupt. A positive transition causes a vector

through the NMI interrupt at location 203Eh. Assert NMI for at

least 1 state time to guarantee acknowledgment by the interrupt

controller.

P0.3

---

Port 0 Pin 3. An input only port pin that is read at location 0Eh

in HWindow 0.

ECB4

---

EDAC Check Bit 4. Asserting the EDACEN pin will cause the

error detection and correction engine to pass the EDAC Check

Bit 4 through pin 4 of the UT80C196KD.

P0.1

---

Port 0 Pin 1. An input only port pin that is read at location 0Eh

in HWindow 0.

ECB31

---

EDAC Check Bit 3. Asserting the EDACEN pin will cause the

error detection and correction engine to pass the EDAC Check

Bit 3 through pin 5 of the UT80C196KD.

P0.0

---

Port 0 Pin 0. An input only port pin that is read at location 0Eh

in HWindow 0.

ECB2

---

EDAC Check Bit 2. Asserting the EDACEN pin will cause the

error detection and correction engine to pass the EDAC Check

Bit 2 through pin 6 of the UT80C196KD.

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