WM8776 datasheet(18/55 Pages) WOLFSON

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WM8776

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PP Rev 1.91 June 2004

AUDIO INTERFACE FORMATS

Audio data is applied to the internal DAC filters or output from the ADC filters, via the Digital

Audio Interface. 5 popular interface formats are supported:

•

Left Justified mode

•

Right Justified mode

•

2S mode

•

DSP Early mode

•

DSP Late mode

All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the

exception of 32 bit right justified mode, which is not supported.

In left justified, right justified and I

2S modes, the digital audio interface receives DAC data on

the DIN input and outputs ADC data on DOUT. Audio Data for each stereo channel is time

multiplexed with ADCLRC/DACLRC indicating whether the left or right channel is present.

ADCLRC/DACLRC is also used as a timing reference to indicate the beginning or end of the

data words.

In left justified, right justified and I

2S modes; the minimum number of BCLKs per

DACLRC/ADCLRC period is 2 times the selected word length. ADCLRC/DACLRC must be

high for a minimum of word length BCLKs and low for a minimum of word length BCLKs. Any

mark to space ratio on ADCLRC/DACLRC is acceptable provided the above requirements

are met.

In DSP early or DSP late mode, DACLRC is used as a frame sync signal to identify the MSB

of the first word. The minimum number of DACBCLKs per DACLRC period is 2 times the

selected word length. Any mark to space ratio is acceptable on DACLRC provided the rising

edge is correctly positioned. The ADC data may also be output in DSP early or late modes,

with ADCLRC used as a frame sync to identify the MSB of the first word. The minimum

number of ADCBCLKs per ADCLRC period is 2 times the selected word length.

LEFT JUSTIFIED MODE

In left justified mode, the MSB of DIN is sampled by the WM8776 on the first rising edge of

DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and

changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the

rising edge of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low

during the right samples (Figure 12).

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 12 Left Justified Mode Timing Diagram

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