WM8776 datasheet(31/55 Pages) WOLFSON

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WM8776

PP Rev 1.91 June 2004

In addition a zero cross detect circuit is provided for the output PGA volume under the control

of bit 7 (ZCEN) in the each attenuation register. When ZCEN is set the attenuation values

are only updated when the input signal to the gain stage is close to the analogue ground

level. This minimises audible clicks and ‘zipper’ noise as the gain values change. A timeout

clock is also provided which will generate an update after a minimum of 131072 master

clocks (= ~10.5ms with a master clock of 12.288MHz). The timeout clock may be disabled by

setting TOD.

Left and right inputs may also be independently muted. The LRBOTH control bit allows the

user to write the same attenuation value to both left and right volume control registers, saving

on software writes. The ADC volume and mute also applies to the bypass signal path.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

7:0

LAG[7:0]

11001111

(0dB)

Attenuation data for Left channel ADC gain in 0.5dB steps. See

Table 15.

R14 (0Eh)

0001110

Attenuation

ADCL

ZCLA

Left channel ADC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

7:0

RAG[7:0]

11001111

(0dB)

Attenuation data for right channel ADC gain in 0.5dB steps. See

Table 15.

R15 (0Fh)

0001111

Attenuation

ADCR

ZCRA

Right channel ADC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

R21 (15h)

0010101

ADC Input Mux

LRBOTH

Right channel input PGA controlled by left channel register

0 : Right channel uses RAG.

1 : Right channel uses LAG.

MUTELA

Mute for left channel ADC

0: Mute Off

1: Mute on

R21 (15h)

0010101

ADC Input Mux

MUTERA

Mute for right channel ADC

0: Mute Off

1: Mute on

ADC HIGHPASS FILTER DISABLE

The ADC digital filters contain a digital high pass filter. This defaults to enabled and can be

disabled using software control bit ADCHPD.

BIT

LABEL

DEFAULT

DESCRIPTION

R11 (0Bh)

0001011

ADC Control

ADCHPD

ADC High pass filter disable:

0: High pass filter enabled

1: High pass filter disabled

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