MAX96708 datasheet(57/68 Pages) MAXIM

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Applications Information

Parallel Interface

The CMOS parallel-interface data width is programmable

and depends on the application. Using a larger width

(BWS = 1) results in a lower-pixel clock rate, while a

smaller width (BWS = 0) allows a higher-pixel clock rate.

Bus Data Width

The bus data width depends on the selected modes. The

available bus width is less when using error detection or

when in double mode (DBL = 1). Table 3 shows the avail-

able bit widths and default mapping for various modes.

Bus Data Rates

The bus data rate depends on the settings BWS and

DBL. Table 4 lists the available PCLK rates available for

different bus-width settings. For lower PCLK rates, set

DBL = 0 (if DBL = 1 in both the serializer and deserializer).

Crossbar Switch

By default, the crossbar switch connects the serializer

input pins DIN_ and HS/VS (when HV encoding is used)

to the corresponding deserializer output pins DOUT_ and

HS/VS when DBL of the serializer and deserializer match.

When there is a DBL mismatch use Table 5, Table 66,

and Table 7 to map the serial bits to the crossbar inputs.

Reprogram the crossbar switch when changing the output

pin assignments.

Crossbar Switch Programming

Each output pin can be assigned any of the 14 DOUT

signals. Multiple outputs can share the same input. To force

an output low, and ignore the input, set CROSSBAR_ bit

= 1110. To force an output high set CROSSBAR_ = 1111.

Recommended Crossbar Switch Programming

Procedure

The following procedure programs the crossbar switch to

reassign input/output pin locations:

1) For the crossbar output equivalent of DOUT0 (XBO0)

select which pin to map (e.g., DOUT4 → XBI4).

2) Set the crossbar bits (CROSSBAR0) to the desired

selected mapped input (e.g., CROSSBAR0 = 0100).

3) Repeat for the other crossbar outputs.

OUTPUT MAPPING

DBL

BWS

PXL_

CRC

HVEN

DOUT11:0, HS, VS

DOUT11:0

DOUT11:0*, HS, VS

DOUT13:0*

DOUT7:0, HS, VS

DOUT7:0

DOUT10:0, HS, VS

DOUT10:0

DOUT11:0*, HS, VS

DOUT13:0*

DOUT11:0*, HS, VS

DOUT13:0*

DOUT11:0*, HS, VS

DOUT13:0*

DOUT11:0*, HS, VS

DOUT13:0*

Table 3. Output-Data Width Selection

*The bit width is limited by the number of available outputs.

Table 4. Data-Rate Selection Table

*Use DRS = 1 with legacy devices only (MAX92XX).

DRS

DBL

BWS

PCLK RANGE (MHZ)

25 to 87

33.3 to 116

12.5 to 43.5

16.7 to 58

6.25 to 12.5

8.33 to 16.7

www.maximintegrated.com

Maxim Integrated │ 57

MAX96708

14-Bit GMSL Deserializer

with Coax or STP Cable Input

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