MPC8240 datasheet(39/52 Pages) MOTOROLA

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MOTOROLA

MPC8240 Integrated Processor Hardware Specifications

System Design Information

Figure 25. COP Connector Diagram

1.7.7

PCI Reference Voltage—LVDD

The MPC8240 PCI reference voltage (LVDD) pins should be connected to 3.3 ±0.3 V power supply if

interfacing the MPC8240 into a 3.3-V PCI bus system. Similarly, the LVDD pins should be connected to

5.0 ±5% V power supply if interfacing the MPC8240 into a 5-V PCI bus system. For either reference

HRESET

HRST_CPU

HRST_CTRL

From Target

Board Sources

HRESET

SRESET 5

VDD_SENSE

5 2

15 3

1 k

Ω

10 k

Ω

10 k

Ω

10 k

Ω

OVDD

CHKSTOP_IN 6

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TRST

(if any)

14 4

Key

Notes:

1. QACK is an output on the MPC8240 and is not required at the COP header for emulation.

2. RUN/STOP normally found on pin 5 of the COP header is not implemented on the MPC8240.

Connect pin 5 of the COP header to OVDD with a 1-kΩ pull-up resistor.

3. CKSTP_OUT normally found on pin 15 of the COP header is not implemented on the MPC8240.

Connect pin 15 of the COP header to OVDD with a 10-kΩ pull-up resistor.

4. Pin 14 is not physically present on the COP header.

QACK 1

OVDD

10 k

Ω

OVDD

TRST

10 k

Ω

OVDD

10 k

Ω

10 k

Ω

5. SRESET functions as output SDMA12 in extended ROM mode.

6. CHKSTOP_IN functions as output SDMA14 in extended ROM mode.

MPC8240

KEY

No pin

COP Connector

Physical Pin Out

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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