MPC8240 datasheet(21/52 Pages) MOTOROLA

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MOTOROLA

MPC8240 Integrated Processor Hardware Specifications

Electrical and Thermal Characteristics

Table 13 provides the I2C output AC timing specifications for the MPC8240.

14, 15

9216, 10240

16, 17, 3A, 3B, 3C, 3D 12288, 14336, 15360, 16384, 20480, 24576

18, 19

18432, 20480

1A, 1B, 3E, 3F

24576, 28672, 30720, 32768

1C, 1D

36864, 40960

1E, 1F

49152, 61440

Notes:

1. Values are in KHz, unless otherwise specified.

2. FDR Hex and Divider (Dec) values are listed in corresponding order.

3. Multiple Divider (Dec) values will generate the same input frequency, but each Divider (Dec) value will generate a

unique output frequency as shown in Table 13.

Table 13. I2C Output AC Timing Specifications

At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V

Num

Characteristic

Min

Max

Unit

Notes

Start condition hold time

(FDR[5] == 0)

× (DFDR/16)/2N + (FDR[5]

== 1)

× (DFDR/16)/2M

—

CLKs

1, 2, 5

Clock low period

DFDR/2

—

CLKs

1, 2, 5

SCL/SDA rise time (from 0.5 to 2.4 V)

—

Data hold time

8.0 + (16

× 2FDR[4:2]) × (5 –

4({FDR[5],FDR[1]} == b'10) –

3({FDR[5],FDR[1]} == b'11) –

2({FDR[5],FDR[1]} == b'00) –

1({FDR[5],FDR[1]} == b'01))

—

CLKs

1, 2, 5

SCL/SDA fall time (from 2.4 to 0.5 V)

—

< 5

Clock high time

DFDR/2

—

CLKs

1, 2, 5

Data setup time (MPC8240 as a

master only)

(DFDR/2) – (Output data hold time)

—

CLKs

1, 5

Start condition setup time (for repeated

start condition only)

DFDR + (Output start condition hold time)

—

CLKs

1, 2, 5

Table 12. MPC8240 Maximum I2C Input Frequency (continued)

FDR Hex 2

Divider 3 (Dec)

Maximum I2C Input Frequency 1

SDRAM_CLK

@ 33 MHz

SDRAM_CLK

@ 50 MHz

SDRAM_CLK

@ 100 MHz

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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