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PC87351 Scheda tecnica(PDF) 39 Page - National Semiconductor (TI) |
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PC87351 Scheda tecnica(HTML) 39 Page - National Semiconductor (TI) |
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39 / 86 page ![]() 2.0 Device Architecture and Configuration (Continued) 39 www.national.com 2.7 PARALLEL PORT - LOGICAL DEVICE 1 2.7.1 General Description The PC87351 Parallel Port device offers a wide range of operational configurations. It utilizes the most advanced protocols in current use, while maintaining full backward compatibility to support existing hardware and software. It supports two Stan- dard Parallel Port (SPP) modes of operation for parallel printer ports, two Enhanced Parallel Port (EPP) modes of operation, and one Extended Capabilities Port (ECP) mode. This versatility is achieved by user software control of the mode in which the device functions. The following table lists the Parallel Port Registers used in each mode of operation. Note: The Parallel Port does not support zero wait states. Table 2-11. Parallel Port Registers Classified by Mode 2.7.2 Configuration 1. These registers are extended, and not standard 1284 registers. They are accessible only when enabled by bit 4 of the Parallel Port Configuration Register (see Section 2.7.3). Offset SPP EPP ECP 00h DTR DTR DATAR (modes 0,1) AFIFO (mode 3) 01h STR STR DSR 02h CTR CTR DCR 03h X ADDR X 04h X DATA0 X 05h X DATA1 X 06h X DATA2 X 07h X DATA3 X 400h X X CFIFO (mode 2) DFIFO (mode 3) TFIFO (mode 6) CNFGA (mode 7) 401h X X CNFGB 402h X X ECR 403h X X EIR1 404h X X EDR1 405h X X EAR1 Index Configuration Register or Action Type Reset 30h Activate. See also bit 0 of the SIOCF1 Register. R/W 00h 60h Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b. R/W 02h 61h Base Address LSB Register. Bits 1 and 0 (for A1 and A0) are read only, 00b. R/W 78h 70h Interrupt Number R/W 07h 71h Interrupt Type Bits 7-2 are read only. Bit 1 is a read/write bit. Bit 0 is read only. It reflects the interrupt type dictated by the Parallel Port operation mode and configured by the Parallel Port Configuration Register. This bit is set to 1 (level interrupt) in Extended Mode and cleared (edge interrupt) in all other modes. R/W 02h 74h DMA Channel Select R/W 04h 75h Report no second DMA assignment RO 04h F0h Parallel Port Configuration Register R/W F2h |
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