PC87351 datasheet(40/86 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.7.3

Parallel Port Configuration Register

This register is reset by hardware to F2h.

Note: For normal operation and to maintain compatibility with future chips, do not change bits 7 through 4.

Location:

Index F0h

Type:

R/W

Usage Hints: Parallel Port modes determine which address bits are used for register addresses. In SPP mode, 14 bits are

used to decode Parallel Port base addresses. In ECP and EPP modes, 13 address bits are used. Table 2-11 shows which

registers and address bits are used in each mode.

The settings of the CTR Register bits listed below control selection of Parallel Port modes, as follows:

• When changing to ECP mode from any other mode, bit 2 must be set to 1, and bits 3 and 4 must be set to 0.

• When changing from SPP to EPP mode, bit 3 must be set to 0.

Bit

76543210

Name

Parallel Port Mode Select

Extended

Access

Reserved

Power

Mode

Control

TRI-STATE

Control

Reset

11110010

Bit

Description

7-5

Parallel Port Mode Select. Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled by bit 4 of the Control2

Conﬁguration Register of the parallel port at offset 02h.

Bits

7 6 5

Mode

0 0 0

SPP Compatible; PD7-0 always output signals

0 0 1

SPP Extended; PD7-0 direction controlled by software

0 1 0

EPP 1.7

0 1 1

EPP 1.9

1 0 0

IEEE1284 (selects IEEE1284 register set), without embedded EPP support

1 0 1

Reserved

1 1 0

Reserved

1 1 1

IEEE1284 (selects IEEE1284 register set), with EPP mode selectable as mode 4 (default)

Extended Register Access

0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored).

1: When ECP is selected by bits 7 through 5, the registers at base (address) + 403h, base + 404h and base +

405h are accessible. This option supports run-time conﬁguration within the Parallel Port address space.

3-2

Reserved

Power Mode Control. When the logical device is active:

0: Parallel port clock disabled

ECP modes and EPP time-out are not functional when the logical device is active. Registers are maintained.

1: Parallel port clock enabled

All operation modes are functional when the logical device is active (default).

TRI-STATE Control. This bit controls the TRI-STATE status of the logical device output pins when it is inactive

(disabled).

0: Disabled (default)

1: Enabled when device inactive

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