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LNBH29 Scheda tecnica(PDF) 9 Page - STMicroelectronics |
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LNBH29 Scheda tecnica(HTML) 9 Page - STMicroelectronics |
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9 / 31 page ![]() DocID023065 Rev 3 9/31 LNBH29 Pin configuration 3 Pin configuration Figure 4. Pin connections QFN16 (3x3) and (4x4) (top view) AM11890v1 GND NC DSQIN/ EXTM VUP NC PGND NC LX SDA ISEL VCC VOUT NC VBYP ADDR SCL 1 2 3 4 5 6 16 15 14 13 7 8 9 12 11 10 Table 2. Pin description Pin n° Symbol Name Pin function 16 LX N-Mos drain Integrated N-channel Power MOSFET drain. 2 P-GND Power ground DC-DC converter power ground. To be connected directly to the Epad. 5 ADDR Address setting Two I²C bus addresses available by setting the address pin level voltage. See Table 11. 6 SCL Serial clock Clock from I²C bus. 7 SDA Serial data Bi-directional data from/to I²C bus. 8 ISEL Current selection The resistor “RSEL” connected between ISEL and GND defines the linear regulator current limit threshold. Refer to Section 2.4. 9 GND Analog ground Analog circuits ground. To be connected directly to the Epad. 10 BYP Bypass capacitor Needed for internal pre-regulator filtering. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of this pin to external current or voltage sources may cause permanent damage to the device. 12 VCC Supply input 8 to 17.5 V IC DC-DC power supply. 13 VOUT LNB output port Output of the integrated very low drop linear regulator. See Table 7 for voltage selection and description. 14 VUP Step-up voltage Input of the linear post-regulator. The voltage on this pin is monitored by the internal step-up controller to keep a minimum dropout across the linear pass transistor. |
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