TMS320VC5421 datasheet(33/104 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS098D

The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the

base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3−4 and

described in Table 3−5.

Reserved

SWSM

R/W=0

LEGEND: R = Read, W = Write

Figure 3−4. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]

Table 3−5. Software Wait-State Control Register (SWCR) Bit Fields

RESET

FUNCTION

NO.

NAME

RESET

VALUE

FUNCTION

15−1

Reserved

These bits are reserved and are unaffected by writes.

SWSM

Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor

of 1 or 2.

- SWSM = 0: wait-state base values are unchanged (multiplied by 1).

- SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.

3.5.2 Programmable Bank-Switching

Programmable bank-switching can be used to insert one cycle automatically when crossing memory-bank

boundaries inside program memory or data memory space. One cycle can also be inserted when crossing

from program-memory space to data-memory space (54x) or one program memory page to another program

memory page. This extra cycle allows memory devices to release the bus before other devices start driving

the bus, thereby avoiding bus contention. The size of the memory bank for the bank-switching is defined by

the bank-switching control register (BSCR), as shown in Figure 3−5. The BSCR of a particular DSP subsystem

(A or B) is used for the external memory interface based on the xDMA/XIO arbitration logic. The BSCR bit

fields are described in Table 3−6.

BNKCMP

PS-DS

Reserved

IPIRQ

Reserved

EXIO

R/W

LEGEND: R = Read, W = Write

Figure 3−5. BSCR Register Bit Layout for Each DSP Subsystem

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