L6985F datasheet(50/65 Pages) STMICROELECTRONICS

50 / 65 page

Application notes

L6985F

50/65

DocID027836 Rev 2

As anticipated above, in the SLAVE mode the internal oscillator operates at 250 kHz typ. but

the slope compensation is dimensioned accordingly with FSW resistors so, even if the

L6985F supports synchronization over the 275 kHz - 1.4 MHz frequency range, it is

important to limit the switching operation around a working point close to the selected

frequency (FSW resistor).

As a consequence, to guarantee the full output current capability and to prevent the

subharmonic oscillations the master must limit the driving frequency range within ± 20% of

the selected frequency.

A wider frequency range may generate subharmonic oscillation for duty > 50% or limit the

peak current capability (see IPK parameter in Table 5 on page 8) since the internal slope

compensation signal may be saturated.

In order to guarantee the synchronization as a slave over distribution, temperature and the

output load, the external clock frequency must be lower than 1.4 MHz.

6.6

Design of the power components

6.6.1

Input capacitor selection

The input capacitor voltage rating must be higher than the maximum input operating voltage

of the application. During the switching activity a pulsed current flows into the input capacitor

and so its RMS current capability must be selected accordingly with the application

conditions. Internal losses of the input filter depends on the ESR value so usually low ESR

capacitors (like multilayer ceramic capacitors) have a higher RMS current capability. On the

other hand, given the RMS current value, lower ESR input filter has lower losses and so

contributes to higher conversion efficiency.

The maximum RMS input current flowing through the capacitor can be calculated as:

Equation 43

Where IOUT is the maximum DC output current, D is the duty cycles, is the efficiency. This

function has a maximum at D = 0.5 and, considering

 = 1, it is equal to IOUT/2.

In a specific application the range of possible duty cycles has to be considered in order to

find out the maximum RMS input current. The maximum and minimum duty cycles can be

calculated as:

Equation 44

Equation 45

Where

VHIGH_SIDE and VLOW_SIDE are the voltage drops across the embedded switches.

IRMS

IOUT



----

–



 D



----



DMAX

VOUT VLOWSIDE

VINMIN VLOWSIDE VHIGHSIDE

–

------------------------------------------------------------------------------------------------

DMIN

VOUT VLOWSIDE

VINMAX VLOWSIDE VHIGHSIDE

–

--------------------------------------------------------------------------------------------------

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