SPC564A80L7 datasheet(13/157 Pages) STMICROELECTRONICS

13 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Introduction

Doc ID 15399 Rev 9

13/157

1.5

Feature details

1.5.1

e200z4 core

SPC564A80 devices have a high performance e200z448n3 core processor:

●

Dual issue, 32-bit Power Architecture embedded category CPU

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Variable Length Encoding Enhancements

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8 KB instruction cache: 2- or 4- way set associative instruction cache

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Thirty-two 64-bit general purpose registers (GPRs)

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Memory management unit (MMU) with 24-entry fully-associative translation look-aside

buffer (TLB)

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Harvard Architecture: Separate instruction bus and load/store bus

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Vectored interrupt support

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Non-maskable interrupt input

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Critical Interrupt input

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New ‘Wait for Interrupt’ instruction, to be used with new low power modes

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Reservation instructions for implementing read-modify-write accesses

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Signal processing extension (SPE) APU

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Single Precision Floating point (scalar and vector)

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Nexus Class 3+ debug

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Process ID manipulation for the MMU using an external tool

1.5.2

Crossbar Switch (XBAR)

The XBAR multiport crossbar switch supports simultaneous connections between five

master ports and four slave ports. The crossbar supports a 32-bit address bus width and a

64-bit data bus width.

The crossbar allows three concurrent transactions to occur from the master ports to any

slave port but each master must access a different slave. If a slave port is simultaneously

requested by more than one master port, arbitration logic selects the higher priority master

and grants it ownership of the slave port. All other masters requesting that slave port are

stalled until the higher priority master completes its transactions. Requesting masters are

treated with equal priority and are granted access to a slave port in round-robin fashion,

based upon the ID of the last master to be granted access. The crossbar provides the

following features:

●

5 master ports

–

CPU instruction bus

–

CPU data bus

–eDMA

–FlexRay

–

External Bus Interface

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