SPC564A80L7 datasheet(21/157 Pages) STMICROELECTRONICS

21 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Introduction

Doc ID 15399 Rev 9

21/157

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SPRAM shared between host CPU and eTPU2, supporting communication either

between channels and host or inter-channel

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Hardware implementation of four semaphores support coherent parameter

sharing between both eTPU engines

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Dual-parameter coherency hardware support allows atomic access to two

parameters by host

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Test and development support features:

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Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction

execution, hardware breakpoints and watchpoints on several conditions

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Software breakpoints

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SCM continuous signature-check built-in self test (MISC - multiple input signature

calculator), runs concurrently with eTPU2 normal operation

1.5.12

Reaction module

The reaction module provides the ability to modulate output signals to manage closed loop

control without CPU assistance. It works in conjunction with the eQADC and eTPU2 to

increase system performance by removing the CPU from the current control loop.

The reaction module has the following features:

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Six reaction channels

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Each channel output is a bus of three signals, providing ability to control 3 inputs.

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Each channel can implement a peak and hold waveform, making it possible to

implement up to six independent peak and hold control channels

Target applications include solenoid control for direct injection systems and valve control in

automatic transmissions

1.5.13

eQADC

The enhanced queued analog to digital converter (eQADC) block provides accurate and fast

conversions for a wide range of applications. The eQADC provides a parallel interface to two

on-chip analog to digital converters (ADC), and a single master to single slave serial

interface to an off-chip external device. Both on-chip ADCs have access to all the analog

channels.

The eQADC prioritizes and transfers commands from six command conversion command

‘queues’ to the on-chip ADCs or to the external device. The block can also receive data from

the on-chip ADCs or from an off-chip external device into the six result queues, in parallel,

independently of the command queues. The six command queues are prioritized with

Queue_0 having the highest priority and Queue_5 the lowest. Queue_0 also has the added

ability to bypass all buffering and queuing and abort a currently running conversion on either

ADC and start a Queue_0 conversion. This means that Queue_0 will always have a

deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs

were performing when the trigger occurred. The eQADC supports software and external

hardware triggers from other blocks to initiate transfers of commands from the queues to the

on-chip ADCs or to the external device. It also monitors the fullness of command queues

and result queues, and accordingly generates DMA or interrupt requests to control data

movement between the queues and the system memory, which is external to the eQADC.

The ADCs also support features designed to allow the direct connection of high impedance

acoustic sensors that might be used in a system for detecting engine knock. These features

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