ST7LITE49K2 datasheet(71/245 Pages) STMICROELECTRONICS

Il numero della parte	ST7LITE49K2

Spiegazioni elettronici	Communication interfaces

PDF	245 Pages

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Produttore elettronici	STMICROELECTRONICS [STMicroelectronics]

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ST7LITE49K2

Power saving modes

71/245

Figure 33.

AWUFH mode flowchart

WDGHALT is an option bit. See option byte section for more details.

Peripheral clocked with an external clock source can still be active.

Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external

interrupt). Refer to Table 18: ST7LITE49K2 interrupt mapping for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and recovered when the CC register is

popped.

RESET

INTERRUPT 3)

CPU

MAIN OSC

PERIPHERALS 2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

MAIN OSC

PERIPHERALS

I[1:0] BITS

OFF

XX 4)

CPU

MAIN OSC

PERIPHERALS

I[1:0] BITS

XX 4)

256 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT 1)

WATCHDOG

RESET

CYCLE

AWU RC OSC

OFF

AWU RC OSC

OFF

HALT INSTRUCTION

(Active-Halt disabled)

(AWUCSR.AWUEN=1)

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