ST7LITE49K2 datasheet(97/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

On-chip peripherals

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Figure 51.

Dynamic DCR2/3 update in one pulse mode

Force update

In order not to wait for the counterx overflow to load the value into active DCRx registers, a

programmable counterx overflow is provided. For both counters, a separate bit is provided

which when set, make the counters start with the overflow value, i.e. FFFh. After overflow,

the counters start counting from their respective auto reload register values.

These bits are FORCE1 and FORCE2 in the ATCSR2 register. FORCE1 is used to force an

overflow on Counter 1 and, FORCE2 is used for Counter 2. These bits are set by software

and reset by hardware after the respective counter overflow event has occurred.

This feature can be used at any time. All related features such as PWM generation, Output

Compare, Input Capture, One-pulse (refer to Figure 51: Dynamic DCR2/3 update in one

pulse mode) etc. can be used this way.

Figure 52.

Force overflow timing diagram

CNTR2

LTIC

000

fcounter2

(DCR2/3)old

(DCR2/3)new

DCR2/3

FORCE2

TRAN2

FFF

(DCR3)old

(DCR3)new

ATR2

000

PWM2/3

extra PWM3 period due to DCR3

update dynamically in one-pulse

mode.

000

FFF

ARRx

E04

E03

fCNTRx

CNTRx

FORCEx

FORCE2 FORCE1

ATCSR2 register

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