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M34E02-F Scheda tecnica(PDF) 19 Page - STMicroelectronics |
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M34E02-F Scheda tecnica(HTML) 19 Page - STMicroelectronics |
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19 / 36 page ![]() DocID10367 Rev 14 19/36 M34E02-F Initial delivery state 4 Initial delivery state The device is delivered with all bits in the memory array set to ‘1’ (each Byte contains FFh). 5 Use within a DDR1/DDR2/DDR3 DRAM module In the application, the M34E02-F is soldered directly in the printed circuit module. The three Chip Enable inputs (E0, E1, E2) must be connected to VSS or VCC directly (that is without using a pull-up or pull-down resistor) through the DIMM socket (see Table 4). The pull-up resistors needed for normal behavior of the I2C bus are connected on the I2C bus of the mother-board (as shown in Figure 11). The Write Control (WC) of the M34E02-F can be left unconnected. However, connecting it to VSS is recommended, to maintain full read and write access. 5.1 Programming the M34E02-F The situations in which the M34E02-F is programmed can be considered under two headings: • when the DDR DRAM is isolated (not inserted on the PCB motherboard) • when the DDR DRAM is inserted on the PCB motherboard 5.1.1 Isolated DRAM module With specific programming equipment, it is possible to define the M34E02-F content, using Byte and Page Write instructions, and its write-protection using the SWP and CWP instructions. To issue the SWP and CWP instructions, the DRAM module must be inserted in a specific slot where the E0 signal can be driven to VHV during the whole instruction. This programming step is mainly intended for use by DRAM module makers, whose end application manufacturers will want to clear this write-protection with the CWP on their own specific programming equipment, to modify the lower 128 Bytes, and finally to set permanently the write-protection with the PSWP instruction. Table 4. DRAM DIMM connections DIMM position E2 E1 E0 0 VSS VSS VSS 1 VSS VSS VCC 2 VSS VCC VSS 3 VSS VCC VCC 4 VCC VSS VSS 5 VCC VSS VCC 6 VCC VCC VSS 7 VCC VCC VCC |
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