AS8C803601 datasheet(11/21 Pages) ALSC

11 / 21 page

AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

ZBT™

™

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial Temperatur e Range

Read Operation with Clock Enable Used(1)

Write Operation with Clock Enable Used(1)

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.

CycleAddressR/W

ADV/LD

CE(2)

CEN

I/O

Comments

nA0

Address and Control meet setup

n+1

Clock n+1 I gnored

n+2

XXX

Clock

V alid

n+3

Clock Ignored, Data Q0 is on the bus.

n+4

Clock Ignored, Data Q0 is on the bus.

n+5

Address A0 Read out (bus trans.)

n+6

Address A1 Read o ut (bus trans.)

n+7

Address A2 Read out (bus trans.)

CycleAddressR/W

ADV/LD

CE(2)

CEN

I/O

Comments

nA0

Address and Control meet setup.

n+1

Clock n+ 1 Ignored.

n+2

Clock Valid.

n+3

Clock Ignored.

n+4

Clock Ignored.

n+5

Write DataD0

n+6

Write DataD1

n+7

Write DataD2

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