AS8C803601 datasheet(7/21 Pages) ALSC

7 / 21 page

6.42

AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

ZBT™

™

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial Temperatur e Range

Synchronous Truth Table(1)

Partial Truth Table for Writes(1)

NOTES:

1. L = V IL, H = V IH, X = Don’t Care.

2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/

signal is ignored when the counter is advanced. Therefore the nature of

the burst cycle (Read or Write) is determined by the status of the R/

signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either ( CE1, or CE2 is sampled high or CE 2 is sampled low) and ADV/ LD is sampled low at rising edge of clock. The data bus will

tri-state two cycles after deselect is initiated.

4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/Os

remains unchanged.

5. To select the chip requires CE1 = L, CE2 = L, CE 2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

7. Q - Data read from the device, D - data written to the device.

NOTES:

1. L = V IL, H = V IH, X = Don’t Care.

2. Multiple bytes may be selected during the same cycle.

3. N/A for X18 configuration.

CEN

R/W

Chip(5)

Enable

ADV/LD

ADDRESS

USED

PREVIOUS CYCLE

CURRENT CYCLE

I/O

(2 cycles later)

Select

Valid

External

LOAD WRITE

D(7)

Select

External

LOAD READ

Q(7)

Valid

Internal

LOAD WRITE /

BURST WRITE

BURSTWRITE

(Advance burst counter)(2)

D(7)

Internal

LOAD READ /

BURSTREAD

(Advance burst counter)(2)

Q(7)

Deselect

DESELECT or STOP(3)

HiZ

DESELECT/ NOOP

NOOP

HiZ

SUSPEND(4)

Previous Value

5304 tbl 08

OPERATION

R/W

BW1

BW2

BW3(3)

BW4(3)

READ

WRITE ALL BYTES

WRITE BYTE 1 (I/O[0:7], I/OP1)(2)

WRITE BYTE 2 (I/O[8:15], I/OP2)(2)

WRITE BYTE 3 (I/O[16:23], I/OP3)(2,3)

WRITE BYTE 4 (I/O[24:31], I/OP4)(2,3)

HHH

RITE

HHH

5304 tbl 09

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