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R5F564MLGDLC Scheda tecnica(PDF) 183 Page - Renesas Technology Corp |
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R5F564MLGDLC Scheda tecnica(HTML) 183 Page - Renesas Technology Corp |
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183 / 228 page ![]() R01DS0173EJ0110 Rev.1.10 Page 183 of 228 Oct 24, 2016 RX64M Group 5. Electrical Characteristics Figure 5.47 RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKB Division Ratio Set to a Value Other Than 1/2) and Simple SPI Timing (Master, CKPH = 1) Figure 5.48 RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKB Division Ratio Set to 1/2) tDr, tDf tSU tH tLEAD tTD tLAG tSSLr, tSSLf tOH tOD MSB IN DATA LSB IN MSB IN MSB OUT DATA LSB OUT IDLE MSB OUT SSLA0 to SSLA3 output RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output MISOA input MOSIA output RSPI SCKn CKPOL = 0 output SCKn CKPOL = 1 output SMISOn input SMOSIn output Simple SPI (n = 0 to 7, 12) tDr, tDf tSU tHF tLEAD tTD tLAG tSSLr, tSSLf tOH tOD MSB IN DATA LSB IN MSB IN MSB OUT DATA LSB OUT IDLE MSB OUT SSLA0 to SSLA3 output RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output MISOA input MOSIA output RSPI tHF |
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