R5F564MLGDLC datasheet(186/228 Pages) RENESAS

186 / 228 page

R01DS0173EJ0110 Rev.1.10

Page 186 of 228

Oct 24, 2016

RX64M Group

5. Electrical Characteristics

Note 1. tPBcyc: PCLKB cycle

Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as groups.

For the QSPI interface, the AC portion of the electrical characteristics is measured for each group.

Figure 5.53

QSPI Clock Timing

Figure 5.54

Transmit/Receive Timing (CPHA = 0)

Table 5.35

QSPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions*2

QSPI

QSPCLK clock cycle

tQScyc

4080

tPBcyc

Figure 5.53

Data input setup time

tSu

6.5

—

Figure 5.54,

Figure 5.55

Data input hold time

tIH

5—

SS setup time

tLEAD

1.5

8.5

tQScyc

SS hold time

tLAG

tQScyc

Data output delay time

tOD

—

10.0

Data output hold time

tOH

–5

—

Successive transmission delay time

tTD

tQScyc

QSPCLK

output

MSB IN

MSB OUT

LSB OUT

IDLE

DATA

LSB IN

DATA

QSSL

output

QSPCLK

CPOL = 0

output

QSPCLK

CPOL = 1

output

QMI,

QIO0 to QIO3

input

QMO,

QIO0 to QIO3

output

tLEAD

tLAG

tSU

tIH

tOH

tOD

tTD

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