ST62T40B datasheet(37/76 Pages) STMICROELECTRONICS

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ST62T40B/E40B

I/O PORTS (Cont’d)

4.1.3 LCD alternate functions (combiports)

PC0 to PC7 can also be individually defined as 8

LCD segment output by setting DDRC, ORC and

DRC registers as shown in Figure 15.

On the contrary with other I/O lines, the reset state

is the LCD output mode. These 8 segment lines are

recognised as S33..S40 by the embedded LCD

controller drive.

4.1.4 SPI alternate functions

PB6/Sin and PB5/Scl pins must be configured as

input through the DDR and OR registers to be

used data in and data clock (Slave mode) for the

SPI. All input modes are available and I/O's can be

read independantly of the SPI at any time.

PB7/Sout must be configured in open drain output

mode to be used as data out for the SPI. In output

mode, the value present on the pin is the port data

output, while serial transmission is possible only in

open drain mode.

Table 15. PC0-PC7 Combiport Option Selection

Note: X = Don’t care

Figure 20. Peripheral Interface Configuration of SPI

DDR

Mode

Option

Input

With pull-up, no interrupt

Input

No pull-up, no interrupt

Input

With pull-up and with interrupt

Input

LCD segment (Reset state)

Output

Open-drain output

Output

Push-pull output

PB7/Sout

PB6/Sin

PB5/Scl

PID

OPR

MUX

OUT

SYNCHRONOUS

SERIAL I/O

CLOCK

PID

PP/OD

VR01661F

609

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