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PRELIMINARY TECHNICAL DATA

AD9953

Control Register Bit Descriptions

Control Function Register #1 (CFR1)

The CFR1 is used to control the various functions, features, and modes of the AD9954. The

functionality of each bit is detailed below.

CFR1<31>: RAM Enable bit.

When CFR1<31> = 0 (default). When CFR1<31> is inactive, the RAM is disabled

for operation. Either Single tone mode of operation or linear sweep mode of

operations is enabled.

When CFR1<31> = 1, if CFR1<31> is active, the RAM is enabled for operation.

Access control for normal operation is controlled via the mode control bits of the

RSCW for the current profile.

CFR1<30>: RAM Destination bit.

CFR1<30> = 0 (default) If CFR1<31> is active, a logic 0 on the RAM Destination

bit (CFR1<30>=0) configures the AD9954 such that RAM output drives the phase

accumulator (i.e. is the frequency tuning word). If CFR1<31> is inactive, CFR1<30>

is a don’t care.

CFR1<30> = 1 If CFR1<31> is active, a logic 1 on the RAM Destination bit

(CFR1<30>=1) configures the AD9954 such that RAM output drives the phase-

offset adder (i.e. sets the phase offset of the DDS core).

CFR1<29:27>: Internal Profile Control bits. These bits cause the Profile Bits to be ignored

and put the AD9954 into an automatic “profile loop sequence” that allows the user to

implement a frequency/phase composite sweep that runs without external inputs. See the

Internal Profile Control section of this document for details.

CFR1<26>: Amplitude ramp rate load control bit.

When CFR1<26> = 0 (default), the amplitude ramp rate timer is loaded only upon

timeout (timer ==1) and is NOT loaded due to an I/O UPDATE input signal.

When CFR1<26> = 1, the amplitude ramp rate timer is loaded upon timeout (timer

==1) or at the time of an I/O UPDATE input signal.

REV. PrB 1/30/03

Page 16

Analog Devices, Inc.

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