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ECT25S40 Scheda tecnica(PDF) 21 Page - E-CMOS Corporation |
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ECT25S40 Scheda tecnica(HTML) 21 Page - E-CMOS Corporation |
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21 / 46 page ![]() E-CMOS Corp. (www.ecmos.com.tw) Page 21 of 46 4L08N-Rev.F001 ECT25S40 4M BIT SPI NOR FLASH Figure 14. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH) Dual I/O Fast Read with “Continuous Read Mode” See Figure 15, the Dual I/O Fast Read instruction can further reduce instruction overhead Through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the“ Continuous Read Mode” bits (M7-0) =AXH, then the next Dual I/O Fast Read instruction (after /CS is raised and then lowered) does not require the BBH instruction code. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next instruction requires the first BBH instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can be used to reset (M7-0) before issuing normal instruction. Figure 15. Dual I/O Fast Read Sequence Diagram (M7-0= AXH) |
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