AD7453BRT-R2 datasheet(6/21 Pages) AD

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AD7453

Rev. B | Page 5 of 20

TIMING SPECIFICATIONS

Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage

level of 1.6 V.

See Figure 2 and the Serial Interface section.

VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.

Table 2.

Parameter

Limit at TMIN, TMAX

Unit

Description

fSCLK1

kHz min

MHz max

tCONVERT

16 × tSCLK

tSCLK = 1/fSCLK

1.6

µs max

tQUIET

ns min

Minimum quiet time between the end of a serial read and the next falling edge of CS

ns min

Minimum CS pulse width

ns min

CS falling edge to SCLK falling edge setup time

t32

ns max

Delay from CS falling edge until SDATA three-state disabled

t42

ns max

Data access time after SCLK falling edge

0.4 tSCLK

ns min

SCLK high pulse width

0.4 tSCLK

ns min

SCLK low pulse width

ns min

SCLK edge to data valid hold time

t83

ns min

SCLK falling edge to SDATA three-state enabled

ns max

SCLK falling edge to SDATA three-state enabled

tPOWER-UP 4

µs max

Power-up time from full power-down

tQUIET

tCONVERT

SCLK

SDATA

4 LEADING ZEROS

THREE-STATE

DB11

DB10

DB2

DB1

DB0

Figure 2. AD7453 Serial Interface Timing Diagram

1 Mark/space ratio for the SCLK input is 40/60 to 60/40.

2 Measured with the load circuit of

and defined as the time required for the output to cross 0.8 V or 2.4 V with V

Figure 3

Figure 3.

= 5 V, and the time required for an output to

cross 0.4 V or 2.0 V for VDD = 3 V.

3 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of

The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

4 See Power-Up Time section.

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